The invention relates to digital-to-analog converters, and in particular, to digital-to-analog converters constructed using charge coupled device technology.
Several techniques are known in the prior art for performing a digital to analog conversion. The most common technique is through the use of a resistor network. Such digital-to-analog converters are usually implemented as hybrid circuits and therefore consume a large amount of space and consume a considerable amount of power. These prior art digital-to-analog converters are therefore relatively expensive in applications such as signal processing where a large number of channels are present. The applications also require a digital-to-analog converter which uses compatible technology with signal processing devices such as demultiplexers, delay lines, transient data records, filters, and processors, and which can be integrated on chip with such devices. Additional problems which are present in signal processing devices which cannot be handled by existing digital-to-analog converters are large variations in the binary input signal levels which require elaborate tuning or trimming of the individual bit elements. Moreover, in some prior art D-A converters, the effects of input signal variations are suppressed by using the input signals to operate arrays of transistors which switch a reference voltage through the resistor network. This requires a large number of separate transistors, some of which require inverted input signals or gated combinations of two or more input signals.
U.S. Pat. No. 4,107,670 describes one type of charged coupled digital-to-analog converter using a reference charge generator for producing charge portions. Such a technique is fairly complicated and not suitable for many applications.
Prior to the present invention there has not been any simple and easy to use digital-to-analog converter using charge coupled device technology.